如何在 SystemVerilog 覆盖组中指定采样延迟

Question

我需要在 posedge 时钟后 1 纳秒对覆盖组中的信号进行采样。这样做的语法是什么？

我的MWE如下：

covergroup DEBUG_CG @ (posedge tb_clock);
  debug_IR : coverpoint dutDevKit.System.debug_1.dmOuter.dmOuter.auto_int_out_0
  {
    bins debug_IR_1 = {1'b1}; 
  }
  debug_ndreset : coverpoint dutDevKit.debug_1.dmOuter.dmOuter.io_ctrl_ndreset
  {
    bins debug_ndreset_1 = {1'b1}; 
  }
endgroup :DEBUG_CG

Answer 1

怎么样：

always @(tb_clock)
  #1 delayed_tb_clock = tb_clock;

covergroup DEBUG_CG @(posedge delayed_tb_clock);

或：

always @(posedge tb_clock) 
  #1 DEBUG_CG0.sample();

covergroup DEBUG_CG;
...
DEBUG_CG DEBUG_CG0 = new();

如何在 SystemVerilog 覆盖组中指定采样延迟

How to specify sample delay in SystemVerilog covergroup

verilog

hdl

register-transfer-level

system-verilog

system-verilog-assertions