如何在 Quartus 中填充双端口 ROM

Question

下面是我的 ROM，我在 .txt 文件中有二进制值，但我不确定如何使用这些值初始化 ROM。我做了一些研究，似乎 .mif 文件是一种方法（但在程序上似乎有点复杂），我发现 $readmemb 作为另一种选择，但它似乎只用于模拟？任何 help/clarification 将不胜感激！

module dual_port_rom (clk, addr_1, addr_2, data_1, data_2);
        
    input clk;
    input [7:0] addr_1;
    input [7:0] addr_2; //check address width!!! and also see how to fill -_-
    output [7:0] data_1;
    output [7:0] data_2;
    reg [7:0] rom [5122:0];
    reg [7:0] read_a1;
    reg [7:0] read_a2;
        
    always @(posedge clk) begin
        read_a1 <= addr_1;
        read_a2 <= addr_2;
    end
    
    assign data_1 = rom[read_a1];
    assign data_2 = rom[read_a2];
    
endmodule

Answer 1

您可以使用$readmemb 或$readmemh 来初始化Quartus 中ROM 的内容。请查看推荐的 HDL 编码样式中的第 1.4.2 节示例 20，以了解建议的 Verilog 以推断双端口 ROM：https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-design-recommendations.pdf；作为参考，您的代码如下所示：

module dual_port_rom (clk, addr_1, addr_2, data_1, data_2);

  input clk;
  input [7:0] addr_1;
  input [7:0] addr_2;
  output reg [7:0] data_1; // Can declare these as reg type directly rather than have an intermediate
  output reg [7:0] data_2;
  reg [7:0] rom [5122:0];

  // From the example, initialize the ROM with $readmemb; which is compatible with simulation making trying out the ROM easier
  initial begin
    $readmemb("init_file.txt", rom);
  end

  always @(posedge clk) begin
    data_1 <= rom[addr_1]; // Following the style from the example, the data should be put into a register once read from the ROM rather than the address. This shouldnt effect the timing of your system since you were putting the address into a register though
    data_2 <= rom[addr_2];
  end
endmodule

请确保您的文件遵循这些函数所期望的正确文件格式，您可以在此处了解更多信息：

如何在 Quartus 中填充双端口 ROM

How to fill-up a dual port ROM in Quartus

verilog

system-verilog

rom

quartus