GND 驱动器从何而来？

Question

请帮我解决quartus中的这个错误。我不知道 GND 驱动器是从哪里来的。

ERROR: The node "filter|input_val[7] has multiple drivers. "non-tri-state driver "filter|input_val[7]$latch" " is one of the multiple drivers". "constant GND" is one of the multiple drivers.

此错误来自 filter|input_val[6]...[0]。

module  simple_fir(clk, reset_n, input_val, output_val);

    parameter               data_width = 8; //width of data input including sign bit
    parameter               size = 1000;    

    input   wire                clk;
    input   wire                reset_n;
    input   reg [(data_width):0]    input_val;
    output  reg [data_width:0]      output_val;
    reg     [(data_width):0]    delayed;
    reg     [data_width:0]      to_avg;     
    reg         [9:0]           ii ;
    reg         [9:0]           i ;
    reg     [data_width:0]      val;
    reg     [data_width:0]      output_arr [(size-1):0];

    logic [(data_width):0] data_from_rom; //precalculated 1 Hz sine wave
    logic [9:0] addr_to_rom;

    initial delayed = 0;
    initial i = 0;
    initial ii = 0;

    //port map to ROM
    rom_data input_data(
    .clk(clk),
    .addr(addr_to_rom), //text file?
    .data(data_from_rom)
    );  

    //Moore FSM

    localparam [3:0]
    s0=0, s1 = 1, s2 = 2, s3 = 3, s4 = 4, s5 = 5, s6 = 6;
    
    reg [3:0] state_reg, state_next;
    initial state_next = 0;

    always @(posedge clk, negedge reset_n) begin
        if (reset_n == 'b0) begin //reset is active low
        state_reg <= s0;
        end else begin
        state_reg <= state_next;
        end
    end         

    always @(state_reg) begin 
        state_next = state_reg; // default state_next
        case (state_reg)

            s0 : begin //initial state, reset state

            if (!reset_n) begin
                output_val <= 0;
                delayed <= 0; 
                to_avg <= 0; 
                i <= 0;
                ii <= 0;
            end else begin
                state_next <= s1;
            end
            end

            s1 : begin

                if (ii>(size-2)) begin
                ii <= 0;
            end else begin
                addr_to_rom <= ii;
                state_next <= s2;
            end
            end

            s2 : begin

            input_val <= data_from_rom;
            ii <= ii+1;
            state_next <= s3;
            end

            s3 : begin

            delayed <= input_val;
            state_next <= s4;
            end

            s4 : begin

            addr_to_rom <= ii;
            state_next <= s5;
            end

            s5 : begin

            input_val <= data_from_rom;
            state_next <= s6;
            end

        s6 : begin
            to_avg <= input_val + delayed; //summing two values
            val <= (to_avg >> 1);   //taking the average
            output_arr[ii-1] <= val; //indexing starts on [2]
            output_val <= val; 
            state_next <= s0;
            end
        endcase
    end 


endmodule

Answer 1

给模块内的 input 端口赋值是非法的:

input_val <= data_from_rom;

GND 驱动器从何而来？

Where would a GND driver come from?

verilog

system-verilog

quartus