是否可以在 io bundle 中声明条件信号?
Is it possible to declare conditionnal signals in io bundle?
是否只有在chisel模块中设置了参数才能声明信号?
喜欢 :
class GbWrite (val debug_simu: Boolean = true) extends Module {
val io = IO(new Bundle {
//...
/* debug */
if(debug_simu){
val countcol = Output(UInt(32.W))
}
})
//...
if(debug_simu) {
io.countcol := pixelCount
}
//...
}
这段代码给我一个错误:
[info] compiling 1 Scala source to /media/stockage/projets/GbVga/chisel/target/scala-2.12/classes ...
[error] /media/stockage/projets/GbVga/chisel/src/main/scala/gbvga/gbwrite.scala:40:8: value countcol is not a member of chisel3.Bundle{val GBHsync: chisel3.Bool; val GBVsync: chisel3.Bool; val GBClk: chisel3.Bool; val GBData: chisel3.UInt; val Maddr: chisel3.UInt; val Mdata: chisel3.UInt; val Mwrite: chisel3.Bool}
[error] io.countcol := pixelCount
[error] ^
[error] one error found
[error] Compilation failed
可以,但您需要使用稍微不同的语法。
参见:How do I create an optional I/O?。问题是您正在创建的条件 val
在 if
的范围内,因此在代码的下方不可见。
是否只有在chisel模块中设置了参数才能声明信号?
喜欢 :
class GbWrite (val debug_simu: Boolean = true) extends Module {
val io = IO(new Bundle {
//...
/* debug */
if(debug_simu){
val countcol = Output(UInt(32.W))
}
})
//...
if(debug_simu) {
io.countcol := pixelCount
}
//...
}
这段代码给我一个错误:
[info] compiling 1 Scala source to /media/stockage/projets/GbVga/chisel/target/scala-2.12/classes ...
[error] /media/stockage/projets/GbVga/chisel/src/main/scala/gbvga/gbwrite.scala:40:8: value countcol is not a member of chisel3.Bundle{val GBHsync: chisel3.Bool; val GBVsync: chisel3.Bool; val GBClk: chisel3.Bool; val GBData: chisel3.UInt; val Maddr: chisel3.UInt; val Mdata: chisel3.UInt; val Mwrite: chisel3.Bool}
[error] io.countcol := pixelCount
[error] ^
[error] one error found
[error] Compilation failed
可以,但您需要使用稍微不同的语法。
参见:How do I create an optional I/O?。问题是您正在创建的条件 val
在 if
的范围内,因此在代码的下方不可见。