Verilog 函数返回错误值

Question

有人可以帮我理解为什么我的功能不能正常工作吗？

module TestBench2();
 
localparam SELECT_NONE   = 0;
localparam SELECT_RAM    = 1;
localparam SELECT_VGA    = 2;
localparam SELECT_UNKNOWN = 8;
 
logic iClk;  
logic reset;
 
logic [ 4 : 0 ] chipSelect;
logic [ 4 : 0 ] requestChipSelect;
logic [ 4 : 0 ] chipSelected;
 
logic oVGAInitReadRequest;
logic oVGALineComplete;
 
initial
begin
  reset = 1;
  oVGAInitReadRequest = 0;
  oVGALineComplete = 0;  
  chipSelected = SELECT_UNKNOWN;
end
 
function automatic logic [ 4 : 0 ] chipSelectFunc;
input requestChipSelect, oVGAInitReadRequest, oVGALineComplete;
 
  if( requestChipSelect == SELECT_VGA )
  begin
    $display( "  requestChipSelect == SELECT_VGA?  -> YES");
    chipSelectFunc = SELECT_VGA;
    chipSelected   = SELECT_VGA;
  end
  else
  if( oVGAInitReadRequest )
  begin
    $display( "  oVGAInitReadRequest?  -> YES");
    chipSelectFunc = SELECT_VGA;
    chipSelected   = SELECT_VGA;
  end
  else
  if( oVGALineComplete )
  begin
    $display( "  oVGALineComplete?  -> YES");
    chipSelectFunc = SELECT_NONE;
    chipSelected   = SELECT_NONE;
  end
  else
  if( requestChipSelect == SELECT_RAM )
  begin
    $display( "  requestChipSelect == SELECT_RAM?  -> YES");
    chipSelectFunc = SELECT_RAM;
    chipSelected   = SELECT_RAM;
  end
  else
  if( requestChipSelect == SELECT_NONE )
  begin
    $display( "  requestChipSelect == SELECT_NONE?  -> YES");
    chipSelectFunc = SELECT_NONE;
    chipSelected   = SELECT_NONE;
  end
  else
  begin
    $display( "requestChipSelect -> STAY SAME");
    // Leave it as-is
    chipSelectFunc = chipSelected;
  end
 
endfunction
 
assign chipSelect = chipSelectFunc( requestChipSelect, oVGAInitReadRequest, oVGALineComplete );
 
integer count = 0;
 
always @( posedge iClk )
begin
  reset = 0;
 
  case( count )
     1: begin
          $strobe ("%2d:requestChipSelect <= SELECT_VGA", count);  
          requestChipSelect <= SELECT_VGA;
        end
 
     2: begin
          $strobe ("%2d:requestChipSelect <= SELECT_NONE", count);
          requestChipSelect <= SELECT_NONE;
        end      
 
     default: begin
          $strobe ("%2d:Default case", count);
        end
  endcase
 
  $strobe ("%2d:chipSelect: %d ", count, chipSelect);  
  count ++;
end
 
endmodule

当我运行上面的代码时，我得到这个作为输出：

# requestChipSelect -> STAY SAME
#  1:Default case
#  1:chipSelect:  8 
#   requestChipSelect == SELECT_NONE?  -> YES
#  2:requestChipSelect <= SELECT_VGA
#  2:chipSelect:  0 
#   requestChipSelect == SELECT_NONE?  -> YES

为什么当requestChipSelect设置为SELECT_VGA时（2），我的函数总是sees/treats this as 0？

Answer 1

因为你已经声明 requestChipSelect 为 1 位宽：

function automatic logic [ 4 : 0 ] chipSelectFunc;
input requestChipSelect, oVGAInitReadRequest, oVGALineComplete;

而不是（例如）5，例如您的 return 值：

function automatic logic [ 4 : 0 ] chipSelectFunc;
input [ 4 : 0 ] requestChipSelect;       
input oVGAInitReadRequest, oVGALineComplete;

Verilog 函数返回错误值

Verilog function returning wrong value

verilog

modelsim

system-verilog