System Verilog 非法分配：无法将解压缩类型分配给压缩类型

Question

我在 System Verilog 中写道：

module mult32x32_arith (
    input logic clk,             // Clock
    input logic reset,           // Reset
    output logic [63:0] product  // Miltiplication product
);

logic left_decoder, right_decoder, product_FF[63:0]={64{1'b0}};

    always_ff @(posedge clk, posedge reset) begin
        if (reset==1'b1)begin
            product <= product_FF;
        end
        else begin
            
        end
    end

但是，我在这一行遇到错误：

product <= product_FF;

它说：

Error: mult32x32_arith.sv(19): Illegal assignment to type 'reg[63:0]' from type 'reg $[63:0]': Cannot assign an unpacked type to a packed type.

但是，我不明白问题是什么。

Answer 1

您声明 product 已打包，product_FF 未打包。请参阅 IEEE Std 1800-2017，第 7.4 节 打包和解包数组:

The term packed array is used to refer to the dimensions declared before the data identifier name. The term unpacked array is used to refer to the dimensions declared after the data identifier name

您需要将它们声明为相同的数据类型。例如，要使它们都打包，请更改：

logic left_decoder, right_decoder, product_FF[63:0]={64{1'b0}};

至：

logic left_decoder, right_decoder;
logic [63:0] product_FF = {64{1'b0}};

System Verilog 非法分配：无法将解压缩类型分配给压缩类型

System Verilog Illegal assignment: Cannot assign an unpacked type to a packed type

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system-verilog