always_ff 块中的综合 for 循环

Question

我想编写以下代码，使其更具可读性和美观性。

always_ff @(posedge clk or negedge rst_n) 
    if(!rst_n)
        line_pipe <= 0;
    else 
        begin
            line_pipe[00] <= Func(inline);
            line_pipe[01] <= Func(line_pipe[00]);
            line_pipe[02] <= Func(line_pipe[01]);
            line_pipe[03] <= Func(line_pipe[02]);
            line_pipe[04] <= Func(line_pipe[03]);
            line_pipe[05] <= Func(line_pipe[04]);
            line_pipe[06] <= Func(line_pipe[05]);
            line_pipe[07] <= Func(line_pipe[06]);
            line_pipe[08] <= Func(line_pipe[07]);
            line_pipe[09] <= Func(line_pipe[08]);
            line_pipe[10] <= Func(line_pipe[09]);
            line_pipe[11] <= Func(line_pipe[10]);
            line_pipe[12] <= Func(line_pipe[11]);
            line_pipe[13] <= Func(line_pipe[12]);
            line_pipe[14] <= Func(line_pipe[13]);
            line_pipe[15] <= Func(line_pipe[14]);
        end

我可以用 for 循环重写这段代码吗？

Answer 1

假设您当前的代码可以合成，那么这也应该可以合成。您可以对 16 项作业中的 15 项使用 for 循环：

always_ff @(posedge clk or negedge rst_n) 
    if(!rst_n)
        line_pipe <= 0;
    else 
        begin
            line_pipe[00] <= Func(inline);
            for (int i=1; i<16; i++) begin
                line_pipe[i] <= Func(line_pipe[i-1]);
            end
        end

always_ff 块中的综合 for 循环

Synthesized for loop in always_ff block

for-loop

verilog

synthesis

function

system-verilog