如何用 4 个触发器制作 4 位环形计数器？

Question

我正在尝试制作这个 4 位环形计数器，我觉得我已经很接近了，但我不知道如何根据前一状态的输出来制作一个输入。这是我拥有的：

`default_nettype none
// Empty top module

module top (
  // I/O ports
  input  logic hz100, reset,
  input  logic [20:0] pb,
  output logic [7:0] left, right
);

  // Your code goes here...
  q[3:0];
  
  assign q[3:0] = right[3:0];
  
  hc74_set setFF(.c(pb[0]), .d(pb[1]), .q(right[0]), .sn(pb[16]));
  hc74_reset resetFF1(.c(pb[0]), .d(pb[1]), .q0(right[1]), .rn(pb[16]));
  hc74_reset resetFF2(.c(pb[0]), .d(pb[1]), .q1(right[2]), .rn(pb[16]));
  hc74_reset resetFF3(.c(pb[0]), .d(pb[1]), .q2(right[3]), .rn(pb[16]));
  
  
endmodule

// Add more modules down here...
// This is a single D flip-flop with an active-low asynchronous set (preset).
// It has no asynchronous reset because the simulator does not allow it.
// Other than the lack of a reset, it is half of a 74HC74 chip.
module hc74_set(input logic d, c, sn,
                  output logic q, qn);
  assign qn = ~q;
  always_ff @(posedge c, negedge sn)
    if (sn == 1'b0)
      q <= 1'b1;
    else
      q <= d;
endmodule

// This is a single D flip-flop with an active-low asynchronous reset (clear).
// It has no asynchronous set because the simulator does not allow it.
// Other than the lack of a set, it is half of a 74HC74 chip.

module hc74_reset(input logic d, c, rn,
                  output logic q, qn);
  assign qn = ~q;
  always_ff @(posedge c, negedge rn)
    if (rn == 1'b0)
      q <= 1'b0;
    else
      q <= d;
endmodule

这是在 FPGA 模拟器上，这就是为什么有一些东西，例如 pb（这些是按钮）和左、右输出，每组 8 个 LED。

Answer 1

让我们首先确保我们在同一页上

基于维基百科对 ring counter

的描述

这可以按如下方式实现：

module top (
  // I/O ports
  input  logic reset_n,
  input  logic clk,
  output logic [3:0] ring
);

  // Your code goes here...
  always @(posedge clk or negedge reset_n) begin
    if(~reset_n) begin
      ring = 4'b0001;
    end
    else begin
      ring[0] <= ring[3];
      ring[1] <= ring[0];
      ring[2] <= ring[1];
      ring[3] <= ring[2];
    end
  end
endmodule

输出环是一个4位的one hot vector，reset_n = 0使得ring = 0001每个带有reset_n = 1的时钟向右滚动环，[0001, 0010, 0100, 1000, 0001, ...].

但是您想使用您定义的触发器的实例。请注意，在赋值 a <= b 中，a 是触发器（q 端口）的输出，b 是触发器（d 端口）的输入。

module top (
  // I/O ports
  input  logic reset_n,
  input  logic clk,
  output logic [3:0] ring
);

  // Your code goes here...
  
  hc74_set setFF(.c(clk), .d(ring[3]), .q(ring[0]), .sn(reset_n));
  hc74_reset resetFF1(.c(clk), .d(ring[0]), .q0(ring[1]), .rn(reset_n));
  hc74_reset resetFF2(.c(clk), .d(ring[1]), .q1(ring[2]), .rn(reset_n));
  hc74_reset resetFF3(.c(clk), .d(ring[2]), .q2(ring[3]), .rn(reset_n));  
endmodule

您必须相应地连接端口，我只是将 clk 用于时钟，将 reset_n 用于取反复位信号。

如何用 4 个触发器制作 4 位环形计数器？

How to make 4 bit ring counter with 4 flip flops?

system-verilog

flip-flop