错误问题 (vlog-2110) 非法引用网络

Question

我正在编写 SystemVerilog 作业来模拟逻辑电路，出现以下错误。我无法理解如何处理它。请帮忙

这些是错误消息：

** Error: E:/ModelSim File/work/1c.sv(8): (vlog-2110) Illegal reference to net "A".
** Error: E:/ModelSim File/work/1c.sv(8): (vlog-2110) Illegal reference to net "B".
** Error: E:/ModelSim File/work/1c.sv(8): (vlog-2110) Illegal reference to net "C".
** Error: E:/ModelSim File/work/1c.sv(10): (vlog-2110) Illegal reference to net "A".
** Error: E:/ModelSim File/work/1c.sv(10): (vlog-2110) Illegal reference to net "B".
** Error: E:/ModelSim File/work/1c.sv(10): (vlog-2110) Illegal reference to net "C".
** Error: E:/ModelSim File/work/1c.sv(12): (vlog-2110) Illegal reference to net "A".
** Error: E:/ModelSim File/work/1c.sv(12): (vlog-2110) Illegal reference to net "B".
** Error: E:/ModelSim File/work/1c.sv(12): (vlog-2110) Illegal reference to net "C".
** Error: E:/ModelSim File/work/1c.sv(14): (vlog-2110) Illegal reference to net "A".
** Error: E:/ModelSim File/work/1c.sv(14): (vlog-2110) Illegal reference to net "B".
** Error: E:/ModelSim File/work/1c.sv(14): (vlog-2110) Illegal reference to net "C".
** Error: E:/ModelSim File/work/1c.sv(16): (vlog-2110) Illegal reference to net "A".
** Error: E:/ModelSim File/work/1c.sv(16): (vlog-2110) Illegal reference to net "B".
** Error: E:/ModelSim File/work/1c.sv(16): (vlog-2110) Illegal reference to net "C".
** Error: E:/ModelSim File/work/1c.sv(18): (vlog-2110) Illegal reference to net "A".
** Error: E:/ModelSim File/work/1c.sv(18): (vlog-2110) Illegal reference to net "B".
** Error: E:/ModelSim File/work/1c.sv(18): (vlog-2110) Illegal reference to net "C".

这是我的代码：

module biii (input logic A,B,C,
output logic F);
assign F = ~(~(A & C) & (B & ~(C)));
endmodule

module t_1c(input logic A,B,C,
output logic F);
biii B2(A,B,C,F);

initial begin

#20
A=0;B=0;C=0;
#20
A=0;B=1;C=0;
#20
A=0;B=0;C=1;
#20
A=1;B=1;C=0;
#20
A=1;B=0;C=0;
#20
A=0;B=1;C=0;
#20;
end
endmodule

Answer 1

t_1c 模块看起来像一个测试平台。在这种情况下，您不需要将信号声明为模块端口。这些错误意味着您无法对模块内声明为 input 端口的信号进行赋值。变化：

module t_1c(input logic A,B,C,
output logic F);

至：

module t_1c;

logic A,B,C,F;

错误问题 (vlog-2110) 非法引用网络

Problem with error (vlog-2110) Illegal reference to net

verilog

system-verilog