延迟计数器不递增？有限状态机

Question

我正在为 DAC 寄存器编写代码，需要延迟。但是，在延迟状态下，DAC_counter_2 并没有递增，也没有实现延迟。我已将代码复制到不同的项目并尝试检查。问题仍然存在。任何帮助都会很棒。

module dac_card
(   output reg DAC_SCLK,
    output reg SYNC,
    output reg SDIN,
    input MHZ_50_CLK,
    input RST,
    output reg [7:0] DAC_counter_1,
    output reg [7:0] DAC_counter_2
    );
    
    reg [7:0] pst_state, nxt_state;
    
    reg [23:0] DAC_reg;
    
    always @(posedge MHZ_50_CLK)
    begin
        if (RST)
        begin
            DAC_reg <= 24'hEEEEEE;
            SYNC <= 1'b1;
            DAC_SCLK <= 1'b0;
            SDIN <=1'b0;
            DAC_counter_1 <= 8'd0;
            DAC_counter_2 <= 8'd0;
            pst_state <= 8'd0;
        end
        else
        begin
            pst_state <= nxt_state;
            DAC_counter_1 <= DAC_counter_1 + 1'b1;
        end
    end
    
    always @(pst_state or DAC_counter_2)
    begin
        case (pst_state)
            8'd0            :   begin
                                    if (DAC_counter_2 == 8'd24)
                                    begin
                                        DAC_counter_2 = 8'd0;
                                        SYNC = 1'b1;
                                        SDIN = 1'b0;
                                        nxt_state = 8'd2;
                                    end
                                    else
                                    begin
                                        SYNC = 1'b0;
                                        DAC_SCLK = 1'b1;
                                        DAC_counter_2 = DAC_counter_2 + 1'b1;
                                        SDIN = DAC_reg [23];                         //Writing DAC register
                                        DAC_reg = DAC_reg << 1;
                                        nxt_state = 8'd1;
                                    end
                                end
            8'd1            :   begin
                                    DAC_SCLK = 1'b0;
                                    nxt_state = 8'd0;
                                end
            8'd2            :   begin
                                    if (DAC_counter_2 == 8'd10)                      //Minimum delay for SYNC to be low for write mode
                                    begin
                                        SYNC = 1'b1;
                                        DAC_counter_2 = 8'd0;
                                        nxt_state = 8'd3;
                                    end
                                    else
                                    begin
                                        SYNC = 1'b0;
                                        //Not incrementing
                                        DAC_counter_2 = DAC_counter_2 + 1'b1;
                                    end                                   
                                end
            8'd3            :   begin
                                    nxt_state = 8'd0;
                                end
            default         :   begin
                                    nxt_state = 8'd0;
                                end
        endcase
    end
endmodule

这里是测试台

module test_bench
();
//Analog Card DAC wires and registers
    reg MHZ_50_CLK;
    reg RST;
    wire DAC_SCLK;
    wire SYNC;
    wire SDIN;
    wire [7:0] DAC_counter_1;
    wire [7:0] DAC_counter_2;
    
    //Instatntiate DAC
    dac_card dc (.DAC_SCLK(DAC_SCLK),
                 .SYNC(SYNC),
                 .SDIN(SDIN),
                 .MHZ_50_CLK(MHZ_50_CLK),
                 .RST(RST),
                 .DAC_counter_1(DAC_counter_1),
                 .DAC_counter_2(DAC_counter_2)
                 );
    initial
    begin
        MHZ_50_CLK = 1'b0;
        #10 RST = 1'b1; 
        #20 RST = 1'b0;
    end
    
    always
    begin
        #10 MHZ_50_CLK <= ~MHZ_50_CLK;
    end
endmodule

这是波形图。在 DAC_counter_2 的 24 次计数后，未实现 8'd10 的延迟。

Answer 1

您需要在 case 语句的所有分支中对 nxt_state 进行赋值。这也避免了推断出无意的闩锁。例如，参考下面的行// MISSING nxt_state =：

        8'd2            :   begin
                                if (DAC_counter_2 == 8'd10)                      //Minimum delay for SYNC to be low for write mode
                                begin
                                    SYNC = 1'b1;
                                    DAC_counter_2 = 8'd0;
                                    nxt_state = 8'd3;
                                end
                                else
                                begin
                                    SYNC = 1'b0;
                                    //Not incrementing
                                    DAC_counter_2 = DAC_counter_2 + 1'b1;
                                    //  MISSING nxt_state =
                                end                                   
                            end

如您的波浪所示，一旦进入状态 2，您将保持状态 2。由于 DAC_counter_2 在状态 2 中不是 10，因此您始终执行 else 子句，该子句不会改变nxt_state.

还有一些其他问题也可能导致问题。

良好的编码习惯建议从单个 always 块分配给 reg。 DAC_counter_2 分配在 2 个不同的块中。

此外，相同的信号不应同时出现在组合 always 块中分配的左轴和右轴上，因为它会创建反馈回路。例如，DAC_counter_2 = DAC_counter_2 + 1 应该像 DAC_counter_1.

这样的顺序 always 块中

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