电线值未正确传递给子模块
Wire value is not passed properly to submodule
我目前遇到一个问题，希望有人能帮助我解决。对于下面测试台中的 VGADesign 模块包装器，为什么电线 (VGA_HS) 和 (VGA_VS) 在我 simulate/run 时显示为 'x' 或未知？我是否没有将值从 DisplayTimings 模块正确传递到 VGADesign 模块？我很迷惑。我在这里面临的问题对我来说并不明显。
测试平台
`timescale 1ns / 1ps
module tb_top();
/////////////////////////// parameter list ///////////////////////////
//CLK: 100MHz
parameter periodCLK_2 = 5;
parameter perioddump = 10;
parameter delay = 1;
parameter delay_in = 2;
parameter VTpw = 1600;
parameter VTdisp = 384000;
parameter VTs = 416800;
parameter VTfp = 23200;
parameter VTbp = 8000;
parameter HTpw = 96;
parameter HTdisp = 640;
parameter HTs = 800;
parameter HTfp = 48;
parameter HTbp = 16;
parameter STpw = 2'h0;
parameter STfp = 2'h1;
parameter STdisp = 2'h2;
parameter STbp = 2'h3;
reg[1:0] HSyncState;
reg[1:0] VSyncState;
reg HStart;
reg CLK_TB;
reg RSTN;
reg [9:0] X_pos;
reg [9:0] Y_pos;
wire[0:0] HSync;
wire[0:0] VSync;
reg de;
integer Clkcount;
integer HSyncCounts;
integer VSyncCounts;
wire VGA_B;
wire VGA_G;
wire VGA_R;
wire VGA_HS;
wire VGA_VS;
wire clk ;
wire clk_out;
clk_div clkdivby4(
.clk(CLK_TB),
.reset(RSTN),
.clk_out(clk_out)
);
DisplayTimings VGATimings(
.Clk_px(clk_out ),
.rst(RSTN),
.sx(),
.sy(),
.Hsync(HSync),
.Vsync(VSync),
.de()
);
VGADesign vga(
.clk_25Mhz(clk_out),
.btn_rst(RSTN),
.vgaHS(VGA_HS),
.vgaVS(VGA_VS),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B)
);
// CLK_TB //
initial
begin
CLK_TB = 1'b0;
#(perioddump);
CLK_TB = 1'b1;
forever
begin
CLK_TB = !CLK_TB;
#(periodCLK_2);
end
end
initial begin
$display("===================");
$display("Start Test Scenario");
$display("===================");
global_reset();
repeat(1) @(posedge CLK_TB); #delay;
repeat(1) @(posedge CLK_TB); #delay;
repeat(10) @(posedge CLK_TB);#delay;
$display(VGA_HS);
$display(VGA_VS);
end
task global_reset;
begin
repeat(2) @(posedge CLK_TB); #delay;
HStart = 1'b0;
VSyncState = 2'h0;
HSyncState = 2'h0;
// VSync = 1'b0;
// HSync = 1'b0;
VSyncCounts=0;
HSyncCounts = 0;
repeat(2) @(posedge CLK_TB); #delay;
RSTN = 1'b0;
repeat(2) @(posedge CLK_TB); #delay;
RSTN = 1'b1;
end
endtask
endmodule
设计
module VGADesign(
input clk_25Mhz, // 25 MHz clock
input btn_rst, // reset button (active low)
output wire[0:0] vgaHS, // horizontal sync
output wire[0:0] vgaVS, // vertical sync
output [3:0] VGA_R, // 4-bit VGA red
output [3:0] VGA_G, // 4-bit VGA green
output [3:0] VGA_B // 4-bit VGA blue
);
DisplayTimings VGATimings(
.Clk_px(clk_25Mhz),
.rst(RSTN),
.sx(),
.sy(),
.Hsync(vgaHS),
.Vsync(vgaVS),
.de()
);
assign VGA_R[0] = 1'b1;
assign VGA_R[1] = 1'b1;
assign VGA_R[2] = 1'b1;
assign VGA_R[3] = 1'b1;
endmodule
module clk_div(
clk,reset, clk_out
);
input clk;
input reset;
output clk_out;
reg [1:0] r_reg;
wire [1:0] r_nxt;
reg clk_track;
always @(posedge clk)
begin
if (!reset)
begin
r_reg <= 3'b0;
clk_track <= 1'b0;
end
else if (r_nxt == 2'b10)
begin
r_reg <= 0;
clk_track <= ~clk_track;
end
else
r_reg <= r_nxt;
end
assign r_nxt = r_reg+1;
assign clk_out = clk_track;
endmodule
`timescale 1ns / 1ps
module DisplayTimings(
input Clk_px, // pixel clock
input rst, // reset
output [9:0] sx, // horizontal screen position
output [9:0] sy, // vertical screen position
output Hsync, // horizontal sync
output Vsync, // vertical sync
output de // data enable (low in blanking interval)
);
reg[0:0] Hsync;
reg[0:0] Vsync;
parameter VTdisp = 384000;
parameter VTpw = 1600;
parameter VTfp = 8000;
parameter VTbp = 23200;
parameter HTdisp = 640;
parameter HTpw = 96;
parameter HTfp = 16;
parameter HTbp = 48;
reg [1:0]Vstate;
reg [1:0]Hstate;
integer Clkcnt;
integer Vcnt;
integer Hcnt;
parameter Vfp = 0, Vpw = 1, Vdisp = 2, Vbp = 3;
parameter Hfp = 0, Hpw = 1, Hdisp = 2, Hbp = 3;
always @(posedge Clk_px or negedge rst) begin
if (!rst) begin
Vcnt = 0;
Hcnt = 0;
Clkcnt =0;
Vsync <= 1'b0;
Hsync <= 1'b0;
Vstate <= Vfp;
Hstate <= Hfp;
end
else begin
case (Vstate)
Vfp: begin
Vcnt = Vcnt+1;
if(Vcnt == VTfp) begin
Vcnt = 0;
Vstate <= Vpw;
Vsync <= 1'b0;
end
end
Vpw: begin
Vcnt = Vcnt+1;
if (Vcnt == VTpw) begin
Vcnt = 0;
Vstate <= Vdisp;
Vsync <= 1'b1;
end
end
Vdisp: begin
Vcnt = Vcnt+1;
if (Vcnt == VTdisp)begin
Vcnt = 0;
Vstate <= Vbp;
end
end
Vbp: begin
Vcnt = Vcnt+1;
if (Vcnt == VTbp) begin
Vcnt = 0;
Vstate <= Vfp;
end
end
endcase
case (Hstate)
Hfp:begin
Hcnt = Hcnt + 1;
if(Hcnt == HTfp) begin
Hcnt = 0;
Hstate <= Hpw;
Hsync <= 1'b0;
end
end
Hpw: begin
Hcnt = Hcnt + 1;
if (Hcnt == HTpw) begin
Hcnt = 0;
Hstate <= Hdisp;
Hsync <= 1'b1;
end
end
Hdisp: begin
Hcnt = Hcnt + 1;
if (Hcnt == HTdisp)begin
Hcnt = 0;
Hstate <= Hbp;
end
end
Hbp:begin
Hcnt = Hcnt + 1;
if (Hcnt == HTbp) begin
Hcnt = 0;
Hstate <= Hfp;
end
end
endcase
end
end
endmodule
信号未知，因为它们没有正确重置。你有一个连接错误。我收到此编译警告：
.rst(RSTN),
|
xmelab: *W,CSINFI : implicit wire has no fanin (tb_top.vga.RSTN).
变化：
.rst(RSTN),
至：
.rst(btn_rst),
这消除了我的未知数。
如果您没有收到类似的警告，您应该在 edaplayground 上尝试您的代码，那里有几个免费的模拟器。
注意：我也看到了其他警告。
我目前遇到一个问题，希望有人能帮助我解决。对于下面测试台中的 VGADesign 模块包装器，为什么电线 (VGA_HS) 和 (VGA_VS) 在我 simulate/run 时显示为 'x' 或未知？我是否没有将值从 DisplayTimings 模块正确传递到 VGADesign 模块？我很迷惑。我在这里面临的问题对我来说并不明显。
测试平台
`timescale 1ns / 1ps
module tb_top();
/////////////////////////// parameter list ///////////////////////////
//CLK: 100MHz
parameter periodCLK_2 = 5;
parameter perioddump = 10;
parameter delay = 1;
parameter delay_in = 2;
parameter VTpw = 1600;
parameter VTdisp = 384000;
parameter VTs = 416800;
parameter VTfp = 23200;
parameter VTbp = 8000;
parameter HTpw = 96;
parameter HTdisp = 640;
parameter HTs = 800;
parameter HTfp = 48;
parameter HTbp = 16;
parameter STpw = 2'h0;
parameter STfp = 2'h1;
parameter STdisp = 2'h2;
parameter STbp = 2'h3;
reg[1:0] HSyncState;
reg[1:0] VSyncState;
reg HStart;
reg CLK_TB;
reg RSTN;
reg [9:0] X_pos;
reg [9:0] Y_pos;
wire[0:0] HSync;
wire[0:0] VSync;
reg de;
integer Clkcount;
integer HSyncCounts;
integer VSyncCounts;
wire VGA_B;
wire VGA_G;
wire VGA_R;
wire VGA_HS;
wire VGA_VS;
wire clk ;
wire clk_out;
clk_div clkdivby4(
.clk(CLK_TB),
.reset(RSTN),
.clk_out(clk_out)
);
DisplayTimings VGATimings(
.Clk_px(clk_out ),
.rst(RSTN),
.sx(),
.sy(),
.Hsync(HSync),
.Vsync(VSync),
.de()
);
VGADesign vga(
.clk_25Mhz(clk_out),
.btn_rst(RSTN),
.vgaHS(VGA_HS),
.vgaVS(VGA_VS),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B)
);
// CLK_TB //
initial
begin
CLK_TB = 1'b0;
#(perioddump);
CLK_TB = 1'b1;
forever
begin
CLK_TB = !CLK_TB;
#(periodCLK_2);
end
end
initial begin
$display("===================");
$display("Start Test Scenario");
$display("===================");
global_reset();
repeat(1) @(posedge CLK_TB); #delay;
repeat(1) @(posedge CLK_TB); #delay;
repeat(10) @(posedge CLK_TB);#delay;
$display(VGA_HS);
$display(VGA_VS);
end
task global_reset;
begin
repeat(2) @(posedge CLK_TB); #delay;
HStart = 1'b0;
VSyncState = 2'h0;
HSyncState = 2'h0;
// VSync = 1'b0;
// HSync = 1'b0;
VSyncCounts=0;
HSyncCounts = 0;
repeat(2) @(posedge CLK_TB); #delay;
RSTN = 1'b0;
repeat(2) @(posedge CLK_TB); #delay;
RSTN = 1'b1;
end
endtask
endmodule
设计
module VGADesign(
input clk_25Mhz, // 25 MHz clock
input btn_rst, // reset button (active low)
output wire[0:0] vgaHS, // horizontal sync
output wire[0:0] vgaVS, // vertical sync
output [3:0] VGA_R, // 4-bit VGA red
output [3:0] VGA_G, // 4-bit VGA green
output [3:0] VGA_B // 4-bit VGA blue
);
DisplayTimings VGATimings(
.Clk_px(clk_25Mhz),
.rst(RSTN),
.sx(),
.sy(),
.Hsync(vgaHS),
.Vsync(vgaVS),
.de()
);
assign VGA_R[0] = 1'b1;
assign VGA_R[1] = 1'b1;
assign VGA_R[2] = 1'b1;
assign VGA_R[3] = 1'b1;
endmodule
module clk_div(
clk,reset, clk_out
);
input clk;
input reset;
output clk_out;
reg [1:0] r_reg;
wire [1:0] r_nxt;
reg clk_track;
always @(posedge clk)
begin
if (!reset)
begin
r_reg <= 3'b0;
clk_track <= 1'b0;
end
else if (r_nxt == 2'b10)
begin
r_reg <= 0;
clk_track <= ~clk_track;
end
else
r_reg <= r_nxt;
end
assign r_nxt = r_reg+1;
assign clk_out = clk_track;
endmodule
`timescale 1ns / 1ps
module DisplayTimings(
input Clk_px, // pixel clock
input rst, // reset
output [9:0] sx, // horizontal screen position
output [9:0] sy, // vertical screen position
output Hsync, // horizontal sync
output Vsync, // vertical sync
output de // data enable (low in blanking interval)
);
reg[0:0] Hsync;
reg[0:0] Vsync;
parameter VTdisp = 384000;
parameter VTpw = 1600;
parameter VTfp = 8000;
parameter VTbp = 23200;
parameter HTdisp = 640;
parameter HTpw = 96;
parameter HTfp = 16;
parameter HTbp = 48;
reg [1:0]Vstate;
reg [1:0]Hstate;
integer Clkcnt;
integer Vcnt;
integer Hcnt;
parameter Vfp = 0, Vpw = 1, Vdisp = 2, Vbp = 3;
parameter Hfp = 0, Hpw = 1, Hdisp = 2, Hbp = 3;
always @(posedge Clk_px or negedge rst) begin
if (!rst) begin
Vcnt = 0;
Hcnt = 0;
Clkcnt =0;
Vsync <= 1'b0;
Hsync <= 1'b0;
Vstate <= Vfp;
Hstate <= Hfp;
end
else begin
case (Vstate)
Vfp: begin
Vcnt = Vcnt+1;
if(Vcnt == VTfp) begin
Vcnt = 0;
Vstate <= Vpw;
Vsync <= 1'b0;
end
end
Vpw: begin
Vcnt = Vcnt+1;
if (Vcnt == VTpw) begin
Vcnt = 0;
Vstate <= Vdisp;
Vsync <= 1'b1;
end
end
Vdisp: begin
Vcnt = Vcnt+1;
if (Vcnt == VTdisp)begin
Vcnt = 0;
Vstate <= Vbp;
end
end
Vbp: begin
Vcnt = Vcnt+1;
if (Vcnt == VTbp) begin
Vcnt = 0;
Vstate <= Vfp;
end
end
endcase
case (Hstate)
Hfp:begin
Hcnt = Hcnt + 1;
if(Hcnt == HTfp) begin
Hcnt = 0;
Hstate <= Hpw;
Hsync <= 1'b0;
end
end
Hpw: begin
Hcnt = Hcnt + 1;
if (Hcnt == HTpw) begin
Hcnt = 0;
Hstate <= Hdisp;
Hsync <= 1'b1;
end
end
Hdisp: begin
Hcnt = Hcnt + 1;
if (Hcnt == HTdisp)begin
Hcnt = 0;
Hstate <= Hbp;
end
end
Hbp:begin
Hcnt = Hcnt + 1;
if (Hcnt == HTbp) begin
Hcnt = 0;
Hstate <= Hfp;
end
end
endcase
end
end
endmodule
信号未知，因为它们没有正确重置。你有一个连接错误。我收到此编译警告：
.rst(RSTN),
|
xmelab: *W,CSINFI : implicit wire has no fanin (tb_top.vga.RSTN).
变化：
.rst(RSTN),
至：
.rst(btn_rst),
这消除了我的未知数。
如果您没有收到类似的警告，您应该在 edaplayground 上尝试您的代码，那里有几个免费的模拟器。
注意：我也看到了其他警告。