Error: Unable to assign to unresolved wires

Question

我编写了一个双向计数器的代码，如果参数 updown=1 则用作向上计数器，否则在 EDAplayground 上使用 icarus verilog 作为我的模拟器用作向下计数器：

module upctr(
  output reg [3:0] num,
  input clock
);
  
  always@(posedge clock)
    begin
      if(num!=4'd9)
        num<= num+4'd1;
      else
        num<= 4'd0;
    end
endmodule

module downctr(
  output reg [3:0] num,
  input clock
);
  
  always@(posedge clock)
    begin
      if(num!=4'd0)
        num<= num-4'd1;
      else
        num<= 4'd9;
    end
endmodule

module testgenerate(
  output reg [3:0] result=4'b0000,
  input clock
);
  parameter updown = 0;
  
  generate
    if(updown)
      upctr uc(result, clock);
    else
      downctr dc(result, clock);
  endgenerate
endmodule

当我执行代码进行排查时，出现了以下错误：

design.sv:31: error: result Unable to assign to unresolved wires.
Elaboration failed
Exit code expected: 0, received: 1

谁能解释一下这个错误的含义以及我该如何更正它？

Answer 1

您的测试台有问题。测试台应该是一个顶级实体，它生成所需的刺激并记录其子模块的结果。因此，您通常不能在测试台中有端口列表，将输入声明为 reg 并将输出声明为 wire。尝试以下更改，对我有用。

`timescale 1ns/1ps

module testgenerate();
 parameter updown = 0;

 reg clock;
 wire [3:0] result;

 initial
  begin
   clock = 1'd0;
   $monitor(result); //This will capture and print any changes to result.
  end

always
#5 clock = ~clock; //Considered a clock with period 10ns.

generate
 if(updown)
  upctr uc(result, clock);
 else
  downctr dc(result, clock);
endgenerate
endmodule

Answer 2

当您不明白错误消息的含义时，您可以在 edaplayground 上的其他模拟器上尝试您的代码。使用 Synopsys VCS，例如：

Error-[ICPSD_INIT] Illegal combination of drivers
  Illegal combination of structural and procedural drivers.
  Variable "result" is driven by an invalid combination of structural and 
  procedural drivers. Variables driven by a structural driver cannot have any 
  other drivers.
  This variable is declared at : reg [3:0] result;
  The first driver is at :  downctr genblk1.dc(result, clock);
  The second driver is at : result = 4'b0;

要修复它，请更改：

output reg [3:0] result=4'b0000,

至：

output [3:0] result,

一种更常见的初始化计数器的方法是在您的设计中添加一个单独的复位输入信号，然后从您的测试台驱动它。例子很多，比如.

Error: Unable to assign to unresolved wires

Error: Unable to assign to unresolved wires

verilog

system-verilog

iverilog