两个不同向量宽度的逻辑相等

Question

为什么两个不同宽度的向量的逻辑相等会产生如下输出？

module eq_test;

logic check;
logic [3:0] cmp_0;
logic       cmp_1 = 1'b0;

initial begin
    for (int i = 0; i < 16; i++) begin
        cmp_0 = i;
        check = (cmp_0 == cmp_1);
        $display("%b == %b is %b", cmp_0, cmp_1, check);
    end
end

endmodule

使用 Vivado 模拟器

0000 == 0 is 1
0001 == 0 is 0
0010 == 0 is 0
0011 == 0 is 0
0100 == 0 is 0
0101 == 0 is 0
0110 == 0 is 0
0111 == 0 is 0
1000 == 0 is 0
1001 == 0 is 0
1010 == 0 is 0
1011 == 0 is 0
1100 == 0 is 0
1101 == 0 is 0
1110 == 0 is 0
1111 == 0 is 0

我可以假设宽度较小的变量cmp_1被扩展（unsigned expand）到较大的变量宽度cmp_0，是这样吗？

Answer 1

是的，宽度较小的变量扩展到较大的变量宽度。

这在 IEEE 标准 1800-2017，第 11.6.1 节中有描述表达式位长度规则。

The number of bits of an expression (known as the size of the expression) shall be determined by the operands involved in the expression and the context in which the expression is given.

在Table11-21中，==运算符有这样的注释：

Operands are sized to max(L(i),L(j))

其中i和j表示操作数的表达式，L(i)表示i.

表示的操作数的位长

所有模拟器都是如此，而不仅仅是 Vivado。

两个不同向量宽度的逻辑相等

Logical equality for two different vector widths

system-verilog

vivado