将 MMIO 外围设备作为子模块添加到 Rocket-chip
Adding an MMIO peripheral to Rocket-chip as a submodule
我按照 MMIO Peripherals page from the Chipyard documentation to learn about adding modules to rocket-chip within Chipyard framework - and all that seems to have worked pretty well. I summed up my experiences and tried to write it in a slower pace on the pages of the Chisel Learning Journey <== 补充说,只有当回答问题的人可能想看一看我的一切是否正常时才添加。换句话说,我在 Chipyard 的 example
包中添加了 MMIO,它编译,生成模拟器,正确响应我设计的玩具基准测试,我什至在 gtkwave 中看到了相应的波形。
现在,我想采取的下一步是将这个虚拟设计(它实际上只是从保存硬编码值的内存映射寄存器中读取)从 chipyard/rocket-chip 基础设施中分离出来,因为它位于一个单独的 repo 中,它将成为我的 chipyard 的一个子模块。所以,为了做到这一点,我从 this page 开始,并采取了那里给出的所有步骤:
- 创建了一个新的存储库,将其命名为
my-chip
- 进入
my-chip
我添加了build.sbt
以下内容:
organization := "My Chip"
version := "1.0"
name := "my-chip"
scalaVersion := "2.12.10"
- 到
my-chip
我添加了 src/main/scala/JustRead.scala
通过学习之旅中提到的页面构建的那个
- 在 JustRead.scala 中,我只替换了
package
行,现在它是:
package my-chip
- 然后,我将
my-chip
存储库作为子模块添加到路径:chipyard/generators/my-chip
- 最后我向
chipyard/generators/chipyard/src/main/scala/DigitalTop.scala
添加了适当的行,如下所示:
package chipyard
import chisel3._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.devices.tilelink._
// ------------------------------------
// BOOM and/or Rocket Top Level Systems
// ------------------------------------
// DOC include start: DigitalTop
class DigitalTop(implicit p: Parameters) extends System
with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port
with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
with my-chip.CanHavePeripheryJustRead // <=== ADDED THIS LINE
with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget
with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget
with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
{
override lazy val module = new DigitalTopModule(this)
}
class DigitalTopModule[+L <: DigitalTop](l: L) extends SystemModule(l)
with testchipip.CanHaveTraceIOModuleImp
with testchipip.CanHavePeripheryBlockDeviceModuleImp
with testchipip.CanHavePeripherySerialModuleImp
with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
with icenet.CanHavePeripheryIceNICModuleImp
with chipyard.example.CanHavePeripheryGCDModuleImp
with my-chip.CanHavePeripheryJustReadTopModuleImp // <=== AND THIS LINE
with freechips.rocketchip.util.DontTouch
// DOC include end: DigitalTop
- 然后,我在
chipyard/generators/chipyard/src/main/scala/configs/RocketConfig.scala
中创建了一个配置如下:
class JustReadTLRocketConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithUART ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithL2TLBs(1024) ++
new my-chip.WithJustRead ++ // <=== THIS LINE ADDED
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
- 最后,我更改了 chipyard 根目录中的主要
build.sbt
以额外保存这些行:
lazy val my-chip = (project in file("generators/my-chip"))
.dependsOn(rocketchip, chisel_testers, midasTargetUtils)
.settings(commonSettings)
和
lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
.dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
sha3, // On separate line to allow for cleaner tutorial-setup patches
my-chip, // <=== ADDED THIS
dsptools, `rocket-dsptools`,
gemmini, icenet, tracegen, ariane, nvdla)
.settings(commonSettings)
现在,当 运行 make CONFIG=JustReadTLRocketConfig
时,我得到以下错误:
OpenJDK 64-Bit Server VM warning: ignoring option MaxPermSize=256M; support was removed in 8.0
Picked up _JAVA_OPTIONS: -Xmx2048m
[info] Loading settings for project chipyard-build from plugins.sbt ...
[info] Loading project definition from /home/apaj/chipyard/project
[error] [/home/apaj/chipyard/build.sbt]:166: Pattern matching in val statements is not supported
环顾四周并没有真正帮助,因为我缺乏任何 scala/software 建筑技能,所以无法充分利用 this,例如...
我的蜘蛛直觉告诉我,我在芯片场内部组织的路径中搞砸了一些东西,所以...请有经验的用户提供一些帮助,我们将不胜感激。谢谢。
编辑:拼写错误并添加第 8 点。
错误来自 lazy val my-chip
和 package my-chip
中的 -
。如果您想在 Scala 名称中使用 -
,您可以将名称用反引号括起来,例如 `my-chip`
.
我按照 MMIO Peripherals page from the Chipyard documentation to learn about adding modules to rocket-chip within Chipyard framework - and all that seems to have worked pretty well. I summed up my experiences and tried to write it in a slower pace on the pages of the Chisel Learning Journey <== 补充说,只有当回答问题的人可能想看一看我的一切是否正常时才添加。换句话说,我在 Chipyard 的 example
包中添加了 MMIO,它编译,生成模拟器,正确响应我设计的玩具基准测试,我什至在 gtkwave 中看到了相应的波形。
现在,我想采取的下一步是将这个虚拟设计(它实际上只是从保存硬编码值的内存映射寄存器中读取)从 chipyard/rocket-chip 基础设施中分离出来,因为它位于一个单独的 repo 中,它将成为我的 chipyard 的一个子模块。所以,为了做到这一点,我从 this page 开始,并采取了那里给出的所有步骤:
- 创建了一个新的存储库,将其命名为
my-chip
- 进入
my-chip
我添加了build.sbt
以下内容:
organization := "My Chip"
version := "1.0"
name := "my-chip"
scalaVersion := "2.12.10"
- 到
my-chip
我添加了src/main/scala/JustRead.scala
通过学习之旅中提到的页面构建的那个 - 在 JustRead.scala 中,我只替换了
package
行,现在它是:
package my-chip
- 然后,我将
my-chip
存储库作为子模块添加到路径:chipyard/generators/my-chip
- 最后我向
chipyard/generators/chipyard/src/main/scala/DigitalTop.scala
添加了适当的行,如下所示:
package chipyard
import chisel3._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.devices.tilelink._
// ------------------------------------
// BOOM and/or Rocket Top Level Systems
// ------------------------------------
// DOC include start: DigitalTop
class DigitalTop(implicit p: Parameters) extends System
with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port
with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
with my-chip.CanHavePeripheryJustRead // <=== ADDED THIS LINE
with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget
with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget
with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
{
override lazy val module = new DigitalTopModule(this)
}
class DigitalTopModule[+L <: DigitalTop](l: L) extends SystemModule(l)
with testchipip.CanHaveTraceIOModuleImp
with testchipip.CanHavePeripheryBlockDeviceModuleImp
with testchipip.CanHavePeripherySerialModuleImp
with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
with icenet.CanHavePeripheryIceNICModuleImp
with chipyard.example.CanHavePeripheryGCDModuleImp
with my-chip.CanHavePeripheryJustReadTopModuleImp // <=== AND THIS LINE
with freechips.rocketchip.util.DontTouch
// DOC include end: DigitalTop
- 然后,我在
chipyard/generators/chipyard/src/main/scala/configs/RocketConfig.scala
中创建了一个配置如下:
class JustReadTLRocketConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithUART ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithL2TLBs(1024) ++
new my-chip.WithJustRead ++ // <=== THIS LINE ADDED
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
- 最后,我更改了 chipyard 根目录中的主要
build.sbt
以额外保存这些行:
lazy val my-chip = (project in file("generators/my-chip"))
.dependsOn(rocketchip, chisel_testers, midasTargetUtils)
.settings(commonSettings)
和
lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
.dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
sha3, // On separate line to allow for cleaner tutorial-setup patches
my-chip, // <=== ADDED THIS
dsptools, `rocket-dsptools`,
gemmini, icenet, tracegen, ariane, nvdla)
.settings(commonSettings)
现在,当 运行 make CONFIG=JustReadTLRocketConfig
时,我得到以下错误:
OpenJDK 64-Bit Server VM warning: ignoring option MaxPermSize=256M; support was removed in 8.0
Picked up _JAVA_OPTIONS: -Xmx2048m
[info] Loading settings for project chipyard-build from plugins.sbt ...
[info] Loading project definition from /home/apaj/chipyard/project
[error] [/home/apaj/chipyard/build.sbt]:166: Pattern matching in val statements is not supported
环顾四周并没有真正帮助,因为我缺乏任何 scala/software 建筑技能,所以无法充分利用 this,例如...
我的蜘蛛直觉告诉我,我在芯片场内部组织的路径中搞砸了一些东西,所以...请有经验的用户提供一些帮助,我们将不胜感激。谢谢。
编辑:拼写错误并添加第 8 点。
错误来自 lazy val my-chip
和 package my-chip
中的 -
。如果您想在 Scala 名称中使用 -
,您可以将名称用反引号括起来,例如 `my-chip`
.