为什么在接口中使用端口？

Question

SystemVerilog LRM (IEEE 1800-2017) 对接口中的端口的描述如下：

One limitation of simple interfaces is that the nets and variables declared within the interface are only used to connect to a port with the same nets and variables. To share an external net or variable, one that makes a connection from outside the interface as well as forming a common connection to all module ports that instantiate the interface, an interface port declaration is required. The difference between nets or variables in the interface port list and other nets or variables within the interface is that only those in the port list can be connected externally by name or position when the interface is instantiated. Interface port declaration syntax and semantics are the same as those of modules (see 23.2.2).

第一句话到底在说什么？我没有看到限制。

第二句中，外部信号的例子是什么？您如何决定信号是应该在接口内部声明还是作为接口的端口声明？ LRM 中使用的文本不适合我。

Answer 1

您引用的 IEEE 1800-2017 SystemVerilog LRM 部分后面的 simple_bus 示例显示了该问题。

接口 sb_intf1 和 sb_intf2 有两个实例，每个实例都创建一组独特的内部信号（req、int、...）。如果 clk 也被声明为内部信号，那么也会有两个时钟信号。示例中未显示的是生成时钟信号的代码。那可能在 top 模块或另一个模块中。他们将需要添加连续分配，以便将生成的时钟信号发送到每个接口实例中的每个内部 clk。

通过将 shared 信号放在其端口声明中的接口中，可以更轻松地加入公共信号。

interface simple_bus (input logic clk); // Define the interface
  logic req, gnt;
  logic [7:0] addr, data;
  logic [1:0] mode;
  logic start, rdy;
endinterface: simple_bus
module memMod(simple_bus a); // Uses just the interface
  logic avail;
  always @(posedge a.clk) // the clk signal from the interface
    a.gnt <= a.req & avail; // a.req is in the 'simple_bus' interface
endmodule
module cpuMod(simple_bus b);
  ...
endmodule
module top;
  logic clk = 0;
  simple_bus sb_intf1(clk); // Instantiate the interface
  simple_bus sb_intf2(clk); // Instantiate the interface
  memMod mem1(.a(sb_intf1)); // Reference simple_bus 1 to memory 1
  cpuMod cpu1(.b(sb_intf1));
  memMod mem2(.a(sb_intf2)); // Reference simple_bus 2 to memory 2
  cpuMod cpu2(.b(sb_intf2));
endmodule

为什么在接口中使用端口？

Why use ports in interfaces?

system-verilog