缺少端口 'v1' 的连接

Question

我正在编写 systemVerilog 代码，其中一个查找值与 8 个相同位大小的寄存器进行比较，如果其中一个寄存器与查找值匹配，它应该给出有效的 1。一切都编译但它给出了几个警告，指出“端口 'v1' 缺少连接”，我不确定如何解决这个问题

下面的代码带有一个简单的测试平台

module V(
input logic [3:0] A,B,
output logic valid);

  logic xnor_3, xnor_2, xnor_1, xnor_0, and_0;
  
  assign xnor_3 = ~(A[3] ^ B[3]);
  assign xnor_2 = ~(A[2] ^ B[2]);
  assign xnor_1 = ~(A[1] ^ B[1]);
  assign xnor_0 = ~(A[0] ^ B[0]);
  assign and_0 = xnor_1 & xnor_0 & xnor_2 & xnor_3 ;
  assign valid = and_0 ;
  
endmodule

module Vt(
input logic[3:0] D_lookup,
input logic[3:0] r0,r1,r2,r3,r4,r5,r6,r7,
output logic v0, v1, v2, v3, v4, v5, v6, v7, Valid);

  V vt0(D_lookup,r0,v0);
  V vt1(D_lookup,r1,v1);
  V vt2(D_lookup,r2,v2);
  V vt3(D_lookup,r3,v3);
  V vt4(D_lookup,r4,v4);
  V vt5(D_lookup,r5,v5);
  V vt6(D_lookup,r6,v6);
  V vt7(D_lookup,r7,v7);

  assign Valid = v0 || v1 || v2 || v3 || v4 || v5 || v6 || v7;
endmodule

module tb_V();
logic[3:0] D_lookup;
logic[3:0] r0,r1,r2,r3,r4,r5,r6,r7;
Vt dut(D_lookup,r0,r1,r2,r3,r4,r5,r6,r7,Valid);
initial begin
D_lookup = 4'b1010;
r0 = 4'b1000;
r1 = 4'b1001;
r2 = 4'b1010;
r3 = 4'b1011;
r4 = 4'b1100;
r5 = 4'b1101;
r6 = 4'b1110;
r7 = 4'b1111; 
#10;
end
endmodule

Answer 1

如果您发布并阅读了您收到的确切错误消息，将会有所帮助

# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'dut'.  Expected 18, found 10.
#    Time: 0 ns  Iteration: 0  Instance: /tb_V/dut File: testbench.sv Line: 36
# ** Warning: (vsim-3722) testbench.sv(36): [TFMPC] - Missing connection for port 'v1'.
# ** Warning: (vsim-3722) testbench.sv(36): [TFMPC] - Missing connection for port 'v2'.
# ** Warning: (vsim-3722) testbench.sv(36): [TFMPC] - Missing connection for port 'v3'.
# ** Warning: (vsim-3722) testbench.sv(36): [TFMPC] - Missing connection for port 'v4'.
# ** Warning: (vsim-3722) testbench.sv(36): [TFMPC] - Missing connection for port 'v5'.
# ** Warning: (vsim-3722) testbench.sv(36): [TFMPC] - Missing connection for port 'v6'.
# ** Warning: (vsim-3722) testbench.sv(36): [TFMPC] - Missing connection for port 'v7'.
# ** Warning: (vsim-3722) testbench.sv(36): [TFMPC] - Missing connection for port 'Valid'.

看来您缺少与 Vt 模块的所有输出端口连接。您需要做的就是添加它们。您甚至不必单独声明它们；将被隐式声明为 1 位线。

  Vt dut(D_lookup,r0,r1,r2,r3,r4,r5,r6,r7,
     v0, v1, v2, v3, v4, v5, v6, v7, Valid );

缺少端口 'v1' 的连接

Missing connection for port 'v1'

modelsim

system-verilog