无法输出输入寄存器的数据

Question

我有一个简单的程序。我正在尝试将计数器输出输入内存地址寄存器并输出内存地址寄存器中的数据。

内存地址注册码：

library ieee;
use ieee.std_logic_1164.all;

entity mar is
port(
    mar_clk, mar_clr, mar_en : in std_logic;
    mar_datain : in std_logic_vector(3 downto 0);
    mar_dataout : out std_logic_vector(3 downto 0)
);
end entity;

architecture behavioral of mar is
begin
    process(mar_clk, mar_clr, mar_en, mar_datain)
        begin
        if(mar_clr = '1') then
            mar_dataout <= (others => '0');
        elsif(mar_clk'event and mar_clk = '1') then
            if(mar_en = '0') then
                mar_dataout <= mar_datain;
            end if;
        end if;
    end process;
end behavioral;

Buffer4 代码：

library ieee;
use ieee.std_logic_1164.all;

entity buffer4 is
port(
    buff4_en : in std_logic;
    datain : in std_logic_vector( 3 downto 0 );
    dataout : out std_logic_vector( 3 downto 0 )
);
end entity;

architecture behavioral of buffer4 is
begin
    process(buff4_en, datain)
    begin
        if(buff4_en = '1') then
            dataout <= datain;
        else
            dataout <= (others => 'Z');
        end if;
    end process;
end behavioral;

程序计数器代码：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pc is
    port(
        pc_ld, pc_en, pc_clk, pc_rst : in std_logic;
        pc_datain : in std_logic_vector(3 downto 0);
        pc_dataout : out std_logic_vector(3 downto 0)
    );
end entity;

architecture behave of pc is
    signal count : std_logic_vector(3 downto 0) := "0001";
    signal temp : integer;
begin
    process(pc_clk, pc_rst)
    begin
        if(pc_rst = '1') then
            count <= (others => '0');
        elsif(pc_clk'event and pc_clk = '1') then
            if(pc_ld = '1') then
                count <= pc_datain;
            elsif(pc_en = '1') then
                count <= count;
                temp <= conv_integer(count);
                if(temp = 16) then
                    count <= (others => '0');
                end if;
                count <= count + 1;
            end if;
        end if;
    end process;
    pc_dataout <= count;
end behave;

测试程序代码：

library ieee;
use ieee.std_logic_1164.all;

entity test is
end entity;

architecture behave of test is

component mar
    port(
        mar_clk, mar_clr, mar_en : in std_logic;
        mar_datain : in std_logic_vector( 3 downto 0 );
        mar_dataout : out std_logic_vector( 3 downto 0 )    
    );
end component;

component pc
    port(
        pc_ld, pc_en, pc_clk, pc_rst : in std_logic;
        pc_datain : in std_logic_vector(3 downto 0);
        pc_dataout : out std_logic_vector(3 downto 0)   
    );
end component;

component buffer4
    port(
        buff4_en : in std_logic;
        datain : in std_logic_vector( 3 downto 0 );
        dataout : out std_logic_vector( 3 downto 0 )    
    );
end component;

signal databus : std_logic_vector(7 downto 0);
signal addressbus : std_logic_vector(3 downto 0);

signal gclk : std_logic;
signal mar_clr, mar_en : std_logic;
signal pc_ld, pc_en, pc_rst : std_logic;

signal buff4_en : std_logic;
signal dataout : std_logic_vector(3 downto 0);

signal mar_datain, mar_dataout : std_logic_vector(3 downto 0);
signal pc_dataout : std_logic_vector(3 downto 0);

begin
    U1 : pc port map(pc_ld, pc_en, gclk, pc_rst, databus(3 downto 0), pc_dataout);
    U2 : buffer4 port map(buff4_en, pc_dataout, databus(3 downto 0));
    U3 : mar port map(gclk, mar_clr, mar_en, databus(3 downto 0), addressbus);

    stim_process : process
    begin
        gclk <= '0';
        wait for 10 ns;
        pc_ld <= '0';
        pc_en <= '1';
        pc_rst <= '0';
        buff4_en <= '1';
        mar_clr <= '0';
        mar_en <= '0';
        gclk <= '1';
        wait for 10 ns;
    
        gclk <= '0';
        wait for 10 ns;
    
        assert false report "Reached end of test. Start GTKWave";
        wait;
    end process;
end behave;

这是我运行程序

时的输出

正如所见，内存地址寄存器接受输入但不在地址总线上输出。如何让内存地址寄存器输出地址总线上的数据？

Answer 1

这是写入 'MAR' 组件内的内存地址输出寄存器的逻辑：

    if(mar_clr = '1') then
        mar_dataout <= (others => '0');
    elsif(mar_clk'event and mar_clk = '1') then
        if(mar_en = '0') then
            mar_dataout <= mar_datain;
        end if;
    end if;

如果在您的时钟上升沿（mar_clk'事件和mar_clk = '1'）出现在波形中 mar_clr 和 mar_en 都是未定义的 U。当上升沿出现时，它们还没有得到它们的值。

您需要重做测试台以确保输入信号在上升沿之前稳定+定义，以便正确采样。然后 mar_dataout <= mar_datain;应该正确服用。

可以尝试像这样移动初始等待语句：

gclk <= '0';
pc_ld <= '0';
pc_en <= '1';
pc_rst <= '0';
buff4_en <= '1';
mar_clr <= '0';
mar_en <= '0';
wait for 10 ns;
gclk <= '1';
wait for 10 ns;

无法输出输入寄存器的数据

Unable to output data entered into a register

vhdl

ghdl

gtkwave