Rocket芯片的复位地址是多少？
What is the reset address for Rocket chip?
RV64G 处理器在复位时从哪个地址开始？
我应该查看哪个 Scala 文件以 understand/modify 重置向量地址？
我尝试为 class Top 中的 TopIO 添加一个简单的 printf 语句
监控 MemIO 并生成模拟器。就绪时，valid = true，地址(io.mem.req_cmd.bits.addr)
打印的是 0x8，标签是 (io.mem.req_cmd.bits.tag) = 0x13。
我可以在程序 rv64ui-p-add.dump
中的地址 0x200 找到获取的指令（在 128 位宽 io.mem.resp.bits.data 中）
所以我假设 0x200 是处理器的起始地址。这是正确的吗？
(a) 如果这是正确的，我想知道，address=0x8 和 tag=0x13 如何转换为 0x200？
(b) 生成的地址 + 标签是 32 位，而我预计它是 64 位（是 RV64G 架构）。在 Configs.scala 中，MIFAddrBits 设置为 26 位（取决于 PAddrBits (32) 和 CacheBlocOffsetBits(log2Up(64))。为什么要这样设置？
(c)
详细模式下仿真器输出中显示的 PC 地址为 40 位，但寄存器为 64 位。
为什么单独显示 PC 地址只有 40 位？仿真器输出的一部分如下所示。
C0: 66 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 67 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 68 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 69 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 70 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Addr (io.mem.req_cmd.bits.addr) - 0x0000008 :: Tag (io.mem.req_cmd.bits.tag) - 0x13 :: rw (io.mem.req_cmd.bits.rw)- 0
C0: 71 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 72 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 73 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 74 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 75 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 76 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 77 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 78 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
...
...
...
C0: 99 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 100 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Mem Response data(io.mem.resp.bits.data) - 0x00054863f000257300051063f1002573 :: Tag (io.mem.resp.bits.tag) - 0x13
C0: 101 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Mem Response data(io.mem.resp.bits.data) - 0x000002975440006f00100e130ff0000f :: Tag (io.mem.resp.bits.tag) - 0x13
C0: 102 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Mem Response data(io.mem.resp.bits.data) - 0x1f8002931012907300028463de428293 :: Tag (io.mem.resp.bits.tag) - 0x13
C0: 103 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Mem Response data(io.mem.resp.bits.data) - 0x3412907301428293000002973002b073 :: Tag (io.mem.resp.bits.tag) - 0x13
C0: 104 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 105 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 106 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 107 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 108 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 109 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 110 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 111 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 112 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 113 [1] pc=[0000000200] W[r10=0000000000000000][1] R[r 0=0000000000000000] R[r16=f4a91906b99f921b] inst=[f1002573] csrr a0, mhartid
C0: 114 [0] pc=[0000000200] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r16=f4a91906b99f921b] inst=[f1002573] csrr a0, mhartid
C0: 115 [0] pc=[0000000200] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r16=f4a91906b99f921b] inst=[f1002573] csrr a0, mhartid
C0: 116 [1] pc=[0000000204] W[r 0=0000000000000000][0] R[r10=0000000000000000] R[r 0=0000000000000000] inst=[00051063] bnez a0, pc + 0
C0: 117 [1] pc=[0000000208] W[r10=8000000000041129][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[f0002573] csrr a0, mcpuid
C0: 118 [0] pc=[0000000208] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[f0002573] csrr a0, mcpuid
C0: 119 [0] pc=[0000000208] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[f0002573] csrr a0, mcpuid
C0: 120 [1] pc=[000000020c] W[r 0=0000000000000001][0] R[r10=8000000000041129] R[r 0=0000000000000000] inst=[00054863] bltz a0, pc + 16
C0: 121 [0] pc=[000000020c] W[r 0=0000000000000001][0] R[r10=0000000000000000] R[r 0=f4a91906b99f921b] inst=[00054863] bltz a0, pc + 16
...
...
...
引用 RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.7（第 3.1.9 节）：
The standard reset vector is either 0xF...FFF00 or 0x0...0200 for high and low locations of the trap vector respectively.
在 Rocket 中，这是通过将 START_ADDR 设置为 0x200 来实现的
src/main/scala/package.scala:
val MTVEC = 0x100
val START_ADDR = MTVEC + 0x100
特权架构仍处于草案阶段，此定义现已更改。
参见 latest privileged ISA spec
我写的V1.10是最新稿。来自“3.3 重置”部分
The pc is set to an implementation-defined reset vector.
因此实现可以为所欲为。
[顺便说一句，本草案在第 3.3 节的一段评论中继续假设重置向量不同于陷阱基向量（在 mtvec 中）。但是正文中并不禁止将它们设置为相同的值。]
RV64G 处理器在复位时从哪个地址开始？ 我应该查看哪个 Scala 文件以 understand/modify 重置向量地址？
我尝试为 class Top 中的 TopIO 添加一个简单的 printf 语句 监控 MemIO 并生成模拟器。就绪时，valid = true，地址(io.mem.req_cmd.bits.addr) 打印的是 0x8，标签是 (io.mem.req_cmd.bits.tag) = 0x13。 我可以在程序 rv64ui-p-add.dump
中的地址 0x200 找到获取的指令（在 128 位宽 io.mem.resp.bits.data 中）所以我假设 0x200 是处理器的起始地址。这是正确的吗？
(a) 如果这是正确的，我想知道，address=0x8 和 tag=0x13 如何转换为 0x200？
(b) 生成的地址 + 标签是 32 位，而我预计它是 64 位（是 RV64G 架构）。在 Configs.scala 中，MIFAddrBits 设置为 26 位（取决于 PAddrBits (32) 和 CacheBlocOffsetBits(log2Up(64))。为什么要这样设置？
(c) 详细模式下仿真器输出中显示的 PC 地址为 40 位，但寄存器为 64 位。 为什么单独显示 PC 地址只有 40 位？仿真器输出的一部分如下所示。
C0: 66 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 67 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 68 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 69 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 70 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Addr (io.mem.req_cmd.bits.addr) - 0x0000008 :: Tag (io.mem.req_cmd.bits.tag) - 0x13 :: rw (io.mem.req_cmd.bits.rw)- 0
C0: 71 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 72 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 73 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 74 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 75 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 76 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 77 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 78 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
...
...
...
C0: 99 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 100 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Mem Response data(io.mem.resp.bits.data) - 0x00054863f000257300051063f1002573 :: Tag (io.mem.resp.bits.tag) - 0x13
C0: 101 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Mem Response data(io.mem.resp.bits.data) - 0x000002975440006f00100e130ff0000f :: Tag (io.mem.resp.bits.tag) - 0x13
C0: 102 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Mem Response data(io.mem.resp.bits.data) - 0x1f8002931012907300028463de428293 :: Tag (io.mem.resp.bits.tag) - 0x13
C0: 103 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
Monitor :: Mem Response data(io.mem.resp.bits.data) - 0x3412907301428293000002973002b073 :: Tag (io.mem.resp.bits.tag) - 0x13
C0: 104 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 105 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 106 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 107 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 108 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 109 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 110 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 111 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 112 [0] pc=[3559fa507b] W[r 0=0000000000000000][0] R[r10=47a548c835ccfca3] R[r17=f91139aacfd283d8] inst=[3d152a9d] c.srli (args unknown)
C0: 113 [1] pc=[0000000200] W[r10=0000000000000000][1] R[r 0=0000000000000000] R[r16=f4a91906b99f921b] inst=[f1002573] csrr a0, mhartid
C0: 114 [0] pc=[0000000200] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r16=f4a91906b99f921b] inst=[f1002573] csrr a0, mhartid
C0: 115 [0] pc=[0000000200] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r16=f4a91906b99f921b] inst=[f1002573] csrr a0, mhartid
C0: 116 [1] pc=[0000000204] W[r 0=0000000000000000][0] R[r10=0000000000000000] R[r 0=0000000000000000] inst=[00051063] bnez a0, pc + 0
C0: 117 [1] pc=[0000000208] W[r10=8000000000041129][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[f0002573] csrr a0, mcpuid
C0: 118 [0] pc=[0000000208] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[f0002573] csrr a0, mcpuid
C0: 119 [0] pc=[0000000208] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[f0002573] csrr a0, mcpuid
C0: 120 [1] pc=[000000020c] W[r 0=0000000000000001][0] R[r10=8000000000041129] R[r 0=0000000000000000] inst=[00054863] bltz a0, pc + 16
C0: 121 [0] pc=[000000020c] W[r 0=0000000000000001][0] R[r10=0000000000000000] R[r 0=f4a91906b99f921b] inst=[00054863] bltz a0, pc + 16
...
...
...
引用 RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.7（第 3.1.9 节）：
The standard reset vector is either 0xF...FFF00 or 0x0...0200 for high and low locations of the trap vector respectively.
在 Rocket 中，这是通过将 START_ADDR 设置为 0x200 来实现的 src/main/scala/package.scala:
val MTVEC = 0x100
val START_ADDR = MTVEC + 0x100
特权架构仍处于草案阶段，此定义现已更改。 参见 latest privileged ISA spec
我写的V1.10是最新稿。来自“3.3 重置”部分
The pc is set to an implementation-defined reset vector.
因此实现可以为所欲为。
[顺便说一句，本草案在第 3.3 节的一段评论中继续假设重置向量不同于陷阱基向量（在 mtvec 中）。但是正文中并不禁止将它们设置为相同的值。]