Verilog error: Range must be bounded by constant expressions

Question

我是 verilog 的新手，我正在为我的 class 做一个项目。所以这是我的代码：

wire [n-1:0] subcounter_of_counter;
reg [n-1:0] mask,free;
//subcounter_of_counter: dinei ena vector apo poious subcounter apoteleitai o counter(id)
always @(*) begin //command or id or mask or free or subcounter_of_counter
if (command==increment) begin
    for (int i = 0; i < n; i=i+1)begin
        if (i<id) begin
            subcounter_of_counter[i]=1'b0;
        end else if (i==id) begin
            subcounter_of_counter[i]=1'b1;
        end else begin
            if( (|mask[id+1:i]) || (|free[id+1:i]) ) begin
                subcounter_of_counter[i]=1'b0;
            end else begin
                subcounter_of_counter[i]=1'b1;
            end
        end
    end
end
end

错误显示 "the range must be bounded by constant expressions."

我还有什么想法可以编写它来执行相同的操作？

非常感谢

Answer 1

您需要做的是创建 mask 和 free 的屏蔽和移位版本。

reg [n-1:0] mask,free,local_mask, local_free;
always @(*) begin //command or id or mask or free or subcounter_of_counter
if (command==increment) begin
    local_mask = mask & ((64'b1<<id+1)-1); // clear bits above id+1
    local_free = free & ((64'b1<<id+1)-1); // clear bits above id+1
    for (int i = 0; i < n; i=i+1)begin
        if (i<id) begin
            subcounter_of_counter[i]=1'b0;
        end else if (i==id) begin
            subcounter_of_counter[i]=1'b1;
        end else begin
            if( (|local_mask) || (|local_free) ) begin
                subcounter_of_counter[i]=1'b0;
            end else begin
                subcounter_of_counter[i]=1'b1;
            end
        end
    end
local_mask = local_mask >> 1; // clear bits below i
local_free = local_free >> 1;
end // for
end // always

我没有尝试过这段代码，但希望它能为您指明正确的方向。

Verilog error: Range must be bounded by constant expressions

Verilog error: Range must be bounded by constant expressions

verilog

system-verilog

digital

digital-logic