verilog 模块中加法器输出的错误值

Question

我已经用Verilog 编写了加法器的门级代码。加法器的输出如下所示。如您所见，sum 和 cout 始终在 z 中。我不知道为什么。你能检查一下我错过了什么吗？谢谢你的时间。

输出：

a = x, b = x, cin = x, summ = z, cout = z 在时间 = 0

a = 0, b = 0, cin = 0, summ = z, cout = z 在时间 = 10

a = 0, b = 1, cin = 0, summ = z, cout = z 在时间 = 20

a = 1, b = 0, cin = 0, summ = z, cout = z 在时间 = 30

a = 1, b = 1, cin = 0, summ = z, cout = z 在时间 = 40

a = 0, b = 0, cin = 1, summ = z, cout = z 在时间 = 50

a = 0, b = 1, cin = 1, summ = z, cout = z 在时间 = 60

a = 1, b = 0, cin = 1, summ = z, cout = z 在时间 = 70

a = 1, b = 1, cin = 1, summ = z, cout = z 在时间 = 80

module tb();  

reg a, b, cin; 
wire cout, summ;


FA_gatelevel gatelevel(.a(a), .b(b), .cin(cin), .summ(summ), .cout(cout));

initial begin  

    #10 a = 0; b = 0; cin = 0; 
    #10 a = 0; b = 1; cin = 0;
    #10 a = 1; b = 0; cin = 0;
    #10 a = 1; b = 1; cin = 0;
    #10 a = 0; b = 0; cin = 1;
    #10 a = 0; b = 1; cin = 1;
    #10 a = 1; b = 0; cin = 1;
    #10 a = 1; b = 1; cin = 1;

end


initial begin


$monitor("a = %0h, b = %0h, cin = %0h, sum = %0h, co = %0h at time = `%0t",a,b,cin,summ,cout,$time); // gate level

    #200 $finish;
end 

endmodule

.

module FA_gatelevel(a, b, cin, summ, cout);

input a,b,cin;
output summ,cout;

FA_co ins_co(.a(a), .b(b), .cin(cin), .cout(cout));
FA_sum ins_sum(.a(a), .b(b), .cin(cin), .summ(summ));

endmodule

.

module FA_co (a, b, cin, cout);

input a, b, cin;
output cout;
wire ab, bc, ca;

and g0 (a,b,ab);
and g1 (b,c,bc);
and g2 (c,a,ca);
or  g3 (ab,bc,ca,cout);

endmodule

.

module FA_sum(a, b, cin, summ);

input a, b, cin;
output  summ;

xor g0 (a,b,cin,summ);


endmodule

Answer 1

连接到 Verilog 门原语时，输出始终是第一个连接。

verilog 模块中加法器输出的错误值

wrong values at adder output in verilog module

verilog

digital-design

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