SystemVerilog Error: variable written by continuous and procedural assignments

Question

我想为我的 ALU 电路创建一个测试台。当我编译它时，出现一些错误：

module ALU_TB();
logic [7:0] A, B, w;
logic [2:0] s, n;
logic co, ci, si;
wire ov, neg, zero, gt, eq;

ALU alu8(A, B, s, si, ci, n, co, ov, zero, neg, gt, eq, w);
assign A = 8'b10000000, B = 8'b0, s = 3'b0, ci = 1'b0, si = 1'b0, n = 3'b011;
initial begin
  integer i;
    for (i = 0; i < 7; i = i + 1) begin 
        s = s + 3'b001;
        repeat(8) #59 A = {A[0], A[7:1]};
        #59 B = 8'b10000000; A = 8'b01011010;
        repeat(8) #59 B = {~B[0], B[7:1]};
    end
end
endmodule

这些是第 12、13、14、14、15 行的编译错误：

** Error: (vlog-3838) variable 's' written by continuous and procedural assignments.

** Error: (vlog-3838) variable'A' written by continuous and procedural assignments.

** Error: (vlog-3838) Variable 'B' written by continuous and procedural assignments.

** Error: (vlog-3838) Variable 'A' written by continuous and procedural assignments.

** Error: (vlog-3838) Variable 'B' written by continuous and procedural assignments.

这些错误是什么意思？

Answer 1

您正在使用 'A'、'B'、'S' 进行连续赋值 (assign) 以及程序块 (initial)。一个变量不能同时用于连续赋值和过程赋值。

顺便说一句，你的代码逻辑不正确。例如，当您分配 B=0 时，这意味着 B 将一直为 0（这就是为什么它被称为连续分配！）。但是你在初始块中更改 B！

您似乎想使用 assign 来初始化信号，但这是完全错误的。初始块用于此目的。

最后，将变量 'i' 的声明放在初始块之外。

integer i;
initial begin
A = 8'b10000000;
 B = 8'b0;
 s = 3'b0;
 ci = 1'b0;
 si = 1'b0;
 n = 3'b011;

    #1 for (i = 0; i < 7; i = i + 1) begin 
        // your code here
    end
end

SystemVerilog Error: variable written by continuous and procedural assignments

SystemVerilog Error: variable written by continuous and procedural assignments

verilog

system-verilog

digital-logic

test-bench