VHDL 计数器返回 'X'，未知值

Question

我正在尝试创建一个带有实例化组件的 4 位计数器，如下所示。当我模拟时，输出在 0 和 X（未知信号）之间切换。我不确定哪里出了问题。仿真、电路图和代码如下所示。

4位模数计数器

位片

    library ieee;
    use ieee.std_logic_1164.all;
    use IEEE.std_logic_unsigned.all;
    use ieee.numeric_std.all;
    use IEEE.std_logic_unsigned.all;
    --======================================================================
    entity counter_BitSlice is
      port (
        CLK    : in  std_logic;
        En     : in  std_logic;
        reset  : in  std_logic;

    OUTPUT   : out std_logic;
    AND_En  : out std_logic
    );
end counter_BitSlice;
--====================================================================
architecture struc of counter_BitSlice is
    signal XOr_En   : std_logic;
    signal En_In    : std_logic;
    signal Result   : std_logic;

begin

counter : process(CLK,XOr_En,reset,Result)
begin

If reset='1' then
XOr_En <='0';
OUTPUT <='0';
AND_En <='0';
Result <='0';
elsif rising_edge(CLK) then
    Result <= XOr_En;
end if;

XOr_En <= En_In XOR Result;
AND_En <= En_In AND Result;
OUTPUT <= Result;

En_In <= En;

end process counter;
end struc;

结构化 VHDL

这里我对切片使用了生成命令，但我对其进行了硬编码以消除错误

library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
--======================================================================
entity counter is

  generic (
    BitLength : natural := 8
    );

  port (
    CLK : in std_logic;
    En_In   : in std_logic;
    reset : in std_logic;
    OUTPUT : out std_logic_vector(3 downto 0);
    A_carry : out std_logic_vector(3 downto 0)

        );

end counter;
--======================================================================
architecture struc of counter is
  component counter_BitSlice
    port(
      CLK                 : in  std_logic;
      En                  : in  std_logic;
      reset               : in std_logic;
      AND_En              : out std_logic;
      OUTPUT              : out std_logic
      );
  end component;
--======================================================================
  signal AND_En_carry     : std_logic_vector(3 downto 0);
  signal OUTPUT_carry     : std_logic_vector(3 downto 0);
begin
--======================================================================
  --CCHV_gen : for i in 1 to (BitLength) generate
  --begin

    CCHV_1 : counter_BitSlice
      port map(
        CLK    => CLK,
        reset  => reset,
        En   => En_In,
        AND_En => AND_En_carry(0),
        OUTPUT  => OUTPUT_carry(0)
        );
        CCHV_2 : counter_BitSlice
      port map(
        CLK    => CLK,
        reset  => reset,
        En   => AND_En_carry(0),
        AND_En => AND_En_carry(1),
        OUTPUT  => OUTPUT_carry(1)
        );
        CCHV_3 : counter_BitSlice
      port map(
        CLK    => CLK,
        reset  => reset,
        En   => AND_En_carry(1),
        AND_En => AND_En_carry(2),
        OUTPUT  => OUTPUT_carry(2)
        );
        CCHV_4 : counter_BitSlice
      port map(
        CLK    => CLK,
        reset  => reset,
        En   => AND_En_carry(2),
        AND_En => AND_En_carry(3),
        OUTPUT  => OUTPUT_carry(3)
        );
 -- end generate CCHV_gen;
    OUTPUT <= OUTPUT_carry;
    A_carry <= AND_En_carry;


  main : process(reset, CLK)
  begin
 if rising_edge(CLK) then 
  if reset ='1' then
  AND_En_carry <= (others=>'0');
  OUTPUT_carry <= (others =>'0');
  end if;
  end if;
  end process;
end architecture struc;

位片测试台

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity tb_counter_BlitSlice is
end tb_counter_BlitSlice;

architecture tb_behav of tb_counter_BlitSlice is

  component counter_BlitSlice
    port(
      CLK                 : in  std_logic;
      En                 : in  std_logic;
      reset         : in std_logic;
      OUTPUT  : out std_logic;
      AND_En : out std_logic
      );
    end component;

  constant t_BitLength : natural :=8;
  signal t_En :std_logic := '0';
  signal t_CLK : std_logic :='0';
  signal t_reset : std_logic :='0';
  signal t_OUTPUT : std_logic :='0';
  signal t_AND_En  : std_logic :='0';

  begin

    U1: counter_BlitSlice
      port map ( 
        CLK => t_CLK,
        reset => t_reset,
        En => t_En,
        OUTPUT => t_OUTPUT,
        AND_En => t_AND_En
        );


    t_CLK <= not t_CLK after 20 ns;
    test : process
    begin
      t_En <= '0';
      t_reset <='0';
      wait for 20 ns;
      t_reset <='1';
      wait for 20 ns;
      t_reset <='0';
      wait for 20 ns;
      t_En <= '0';
      wait for 40 ns;
      t_En <= '1';
      wait for 20 ns;
      wait;
      end process test;
    end architecture tb_behav;

计数器测试台

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_unsigned.all;

entity tb_counter is
end tb_counter;

architecture tb_behav of tb_counter is

  component counter
  generic(
        BitLength : natural :=8
    );
    port(
      CLK                 : in  std_logic;
      En_In                 : in  std_logic;
      reset         : in std_logic;
      OUTPUT  : out std_logic_vector(3 downto 0);
      A_carry : out std_logic_vector(3 downto 0)
      );
    end component;

  constant t_BitLength : natural :=8;
  signal t_En :std_logic := '0';
  signal t_CLK : std_logic :='0';
  signal t_reset : std_logic :='0';
  signal t_OUTPUT : std_logic_vector(3 downto 0) := (others =>'0');
  signal t_ANDcarry : std_logic_vector(3 downto 0) := (others =>'0');

  begin

    U1: counter
    generic map(
        BitLength => t_BitLength
    )
      port map ( 
        CLK => t_CLK,
        reset => t_reset,
        En_In => t_En,
        OUTPUT => t_OUTPUT,
        A_carry => t_ANDcarry
        );


    t_CLK <= not t_CLK after 20 ns;
    test : process
    begin
      t_En <= '0';
      t_reset <='0';
      wait for 20 ns;
      t_reset <='1';
      wait for 80 ns;
      t_reset <='0';
      wait for 60 ns;
      t_En <= '0';
      wait for 40 ns;
      t_En <= '1';
      wait for 20 ns;
      wait;
      end process test;
    end architecture tb_behav;

当我模拟位片时，输出正确切换，如下所示。

计数器模拟的位片

并且当我模拟组合计数器以获得四位计数器时，它会在无符号值之间切换，如下所示。我不明白这是什么问题。

计数器模拟

2:

我在 control.vhd 中取出了重置，这消除了未知信号，但它没有正确计数。如下所示。

Answer 1

我在修改 slice_counter 代码后让它工作了。

counter : process(CLK,reset)
begin

If reset='1' then
    OUTPUT <='0';
    Result <='0';
elsif rising_edge(CLK) then
    OUTPUT <= XOr_En;
   Result <= XOr_En;
end if;

end process counter;

XOr_En <= En XOR Result;
AND_En <= En AND Result;

end struc;

您应该将 AND 和 XOR 门放在进程之外。那是导致错误的原因。

VHDL 计数器返回 'X'，未知值

VHDL Counter returning 'X', unknown value

binary

vhdl

counter

vlsi

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