Compilation error: A net is not a legal lvalue in this context

Question

我是 Verilog 的新手，在定义 if-else 循环时遇到了问题。错误信息是

A net is not a legal lvalue in this context" for all assign statements in the given code.

always @(adbar)  
if (adbar==1'b1)  
  begin   
    assign Z[0] = m_out[0];  
    assign Z[1] = m_out[1];  
    assign Z[2] = m_out[2];  
    assign Z[3] = X[5];  
    assign Z[4] = X[6];  
    assign Z[5] = X[7];  
    assign Z[6] = m_out[3]; 
    assign Z[7] = m_out[4];  
  end  
  else   
  begin    
    assign Z[0] = m_out[0];  
    assign Z[1] = m_out[1];  
    assign Z[2] = m_out[2];  
    assign Z[3] = X[3];  
    assign Z[4] = X[4];  
    assign Z[5] = X[5];   
    assign Z[6] = m_out[3];  
    assign Z[7] = m_out[4];  
  end  
endmodule

完整程序如下。所有模块都已正确定义，我确定错误仅在这部分。

 module my_decoder (X,adbar, clear, clock, Z);  
 input [7:0] X;  
 input adbar; 
 input clear, clock;  
 output [7:0] Z;  

 wire clear, clock;  
 wire [7:0] Z; 
 wire [4:0] d_out;  
 wire [4:0] x_out;  
 wire [4:0] m_out;  
 wire [4:0] n_out;  
 wire sel1;  
 wire c_out1;  
 wire c_out2;  
 wire c_out3;  

 mux2_gate_1 \dut6[0].l4 (.in1 (x_out[0]), .in2 (n_out[0]), .sel (sel1), .o(m_out[0]));  
 mux2_gate_2 \dut6[1].l4 (.in1 (x_out[1]), .in2 (n_out[1]), .sel (sel1), .o(m_out[1]));  
 mux2_gate_3 \dut6[2].l4 (.in1 (x_out[2]), .in2 (n_out[2]), .sel (sel1), .o(m_out[2]));  
 mux2_gate_4 \dut6[3].l4 (.in1 (x_out[3]), .in2 (n_out[3]), .sel (sel1), .o(m_out[3]));  
 mux2_gate_5 \dut6[4].l4 (.in1 (x_out[4]), .in2 (n_out[4]), .sel (sel1), .o(m_out[4]));  

 always @(adbar)  
 if (adbar==1'b1)  
 begin   
   assign Z[0] = m_out[0];  
   assign Z[1] = m_out[1];  
   assign Z[2] = m_out[2];  
   assign Z[3] = X[5];  
   assign Z[4] = X[6];  
   assign Z[5] = X[7];  
   assign Z[6] = m_out[3]; 
   assign Z[7] = m_out[4];  
 end  
 else   
 begin    
   assign Z[0] = m_out[0];  
   assign Z[1] = m_out[1];  
   assign Z[2] = m_out[2];  
   assign Z[3] = X[3];  
   assign Z[4] = X[4];  
   assign Z[5] = X[5];   
   assign Z[6] = m_out[3];  
   assign Z[7] = m_out[4];  
 end  
endmodule

Answer 1

在 Verilog 中，您可以使用 assign 或 always 对组合电路建模。你不能把它们混在一起。

如果您想使用 assign 建模，您可以将 always 块替换为以下结构：

assign Z = adbar ? {m_out[4:3], X[7:5], m_out[2:0]} : {m_out[4:3], X[5:3], m_out[2:0]};

如果您想使用 always 建模，请从赋值中删除 assign 关键字并将 Z 输出类型从 wire 更改为 reg。

Compilation error: A net is not a legal lvalue in this context

Compilation error: A net is not a legal lvalue in this context

verilog

asic

digital-design