使用两个 4 CLA 的 Questasim 中的 SystemVerilog 出现 8 位进位超前加法器错误

Question

我在模拟CLA4Top、CLA8Top 和测试时总是报错。给出了测试平台，编译了整个项目。对于 CLA4Top，我认为“cout”看起来是正确的，但“sum”与预期输出不匹配。我更改了它，这是更新后的代码：

这是CLA4Top.sv

//4 bit carry lookahead adder
module CLA4Top(ain, bin, cin, sum, cout);
//parameter nBITS = 4;
//logic [nBITS - 1 : 0] ain, bin, sum;
//logic cin, cout;
input [3:0] ain, bin;
input cin;
output logic [3:0] sum;
output logic cout;

CLA4Bit C1(.*);
test #(4) TB(.*);

endmodule


module CLA4Bit (ain, bin, cin, sum, cout);
timeunit 1ns/1ns;
input [3:0] ain, bin;
input cin;
output logic [3:0] sum;
output logic cout;
wire p0,p1,p2,p3,g0,g1,g2,g3,c1,c2,c3,c4,c0;

assign p0=(ain[0]^bin[0]),
       p1=(ain[1]^bin[1]),
       p2=(ain[2]^bin[2]),
       p3=(ain[3]^bin[3]);

assign g0=(ain[0]&bin[0]),
       g1=(ain[1]&bin[1]),
       g2=(ain[2]&bin[2]),
       g3=(ain[3]&bin[3]);
       
assign c0=cin,
       c1=g0|(p0&cin),
       c2=g1|(p1&g0)|(p1&p0&cin),
       c3=g2|(p2&g1)|(p2&p1&g0)|(p1&p1&p0&cin),
       c4=g3|(p3&g2)|(p3&p2&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&cin);
       
assign sum[0] = ain[0] ^ bin[0] ^ cin,
  sum[1] = ain[1] ^ bin[1] ^ c1,
      sum[2] = ain[2] ^ bin[2] ^ c2,
      sum[3] = ain[3] ^ bin[3] ^ c3;
       
assign cout=c4;


         
endmodule

这是CLA8Top.sv

// module with 8 bit adder using 4 bit CLA instances

module CLA8Top(ain, bin, cin, sum, cout);
//parameter nBITS = 8;

input [7:0] ain, bin;
input cin;
output logic [7:0] sum;
output logic cout;

wire c1;

// CLA4Bit c11(ain[3:0],bin[3:0],1'b0,sum[3:0],c1);
CLA4Bit c11(ain[3:0],bin[3:0],cin,sum[3:0],c1);
CLA4Bit c22(ain[7:4],bin[7:4],c1,sum[7:4],cout);
test #(8) TB(.*);

endmodule

这是 testbench.sv

// Test bench for Generic N-Bits Adder design module

module test(ain, bin, cin, sum, cout);

timeunit 1ns/1ns;
parameter nBITS = 4;
parameter DELAY = 100;
input [nBITS - 1 : 0] sum;
input cout;
 
output [nBITS - 1 : 0] ain, bin;
output cin;

logic [nBITS - 1 : 0] ain, bin, sum;
logic cin, cout;

// test variables
logic [nBITS : 0] exp_value;
int i, j, test_count;
bit error;

initial begin
    error       = 0;
    test_count  = 0;
    cin         = 0;
    repeat(2) begin
        for(i = 0; i < (1 << nBITS); i++) begin
        ain = i;
        for(j = 0; j < (1 << nBITS); j++) begin
        test_count++;
        bin = j;
        exp_value = ain + bin + cin;
        #DELAY;
        if({cout, sum} !== exp_value) begin
        $display("For inputs: ain = %b, bin = %b, cin = %b :: Actual outputs: cout = %1b, sum = %b :: Expected outputs: cout = %1b, sum = %b", ain, bin, cin, cout, sum, exp_value[nBITS], exp_value[nBITS-1:0]);
        error = 1;
        end // end for if block
        end // end for j for loop
        end // end for i for loop
        cin = ~cin;
    end // end for repeat block

    if(error === 0) 
        $display("***Congratulations, No errors found after %d tests***", test_count);
    else
        $display("***Sorry, errors found in your code ***");
end // end for initial block


endmodule

我是否可以进行任何更改，使我得到您可以看到的 $display("***Congratulations, No errors found after %d tests***", test_count);？我有什么问题，为什么？我将包括运行和 CLA4Top.sv 的成绩单。

Answer 1

日志文件显示 sum[3] 与预期值不匹配。 c3 的等式中有错字。变化：

   c3=g2|(p2&g1)|(p2&p1&g0)|(p1&p1&p0&cin),
                             //

至：

   c3=g2|(p2&g1)|(p2&p1&g0)|(p2&p1&p0&cin),
                             //

使用两个 4 CLA 的 Questasim 中的 SystemVerilog 出现 8 位进位超前加法器错误

8 bit carry lookahead adder error with SystemVerilog in Questasim using two 4 CLA's

verilog

system-verilog

digital-logic

questasim